Feature scaling in integrated circuits is an enabler of more capable electronic devices. Scaling to smaller features increases densities of functional units in a given form factor as well as increasing device processing speeds. Device scaling, however, is not without issue. For example, optimizing the performance of smaller devices becomes increasingly difficult. This is particularly true for the scaling of nonvolatile charge trap memory devices, in which data retention and sensing becomes increasingly difficult as the devices are scaled.
In addition to device scaling, system-on-a-chip type architecture also increases electronic device functionality. Such architecture may incorporate, for example, a memory device on the same substrate as a logic device to reduce the cost of fabrication as well as increase communication bandwidth between the memory and logic devices.
The integration of these dissimilar devices in a system-on-a-chip architecture is problematic because the fabrication process for the logic MOS device may hamper the fabrication process of the memory device and vice versa. Such a dilemma may occur, for example, when integrating the logic MOS gate oxide process module with the fabrication of a dielectric stack for a memory device. Also, channel and well implant processing for the logic devices may also be detrimental to the memory device dielectric stack while formation of the latter may be problematic for the former. As still another example, silicided contacts, which are advantageous for a logic transistor, may adversely affect a nonvolatile charge trap memory device.
Also, operation of a non-volatile memory device may require application of relatively high voltages (HV), typically of at least 10 V. However, the conventional processes employed in fabrication of a scaled logic device are typically optimized for device operation at 5 V or less. Such low voltage devices may lack a sufficiently high breakdown voltage to interface directly with a memory device.